How to take Dynamic power and switching power report using design complier or prime time synopsys tool?
How to take input based switching activity power in virtex FPGA kit?
Power analysis report file we will find dynamic and leakage power. the write command should be given in tcl script ......compile -map_effort medium -area_effort low -power_effort high......source ./DC_scripts/report.tcl...
set maxpaths 100
check_design > "./reports/${rpt_file}"
report_area >> "./reports/${rpt_file}"
report_design >> "./reports/${rpt_file}"
report_cell >> "./reports/${rpt_file}"
report_reference >> "./reports/${rpt_file}"
report_port -verbose >> "./reports/${rpt_file}"
report_net -verbose >> "./reports/${rpt_file}"
report_compile_options >> "./reports/${rpt_file}"
report_constraint -all_violators >> "./reports/{rpt_file}"
report_net -noflat -transition_times -cell_degradation -connection >> "./reports/${rpt_file}"
report_timing >> "./reports/${rpt_file}"
report_timing -path end >> "./reports/${rpt_file}"
report_timing -max_path $maxpaths >> "./reports/${rpt_file}"
report_qor >> "./reports/${rpt_file}"
report_power -verbose >> "./reports/${rpt_file}"
fpga kit we have different kit called as sabero if not mistaken which will give switching for a input vector.
The question is a bit confusing. PrimeTime is a timing analysis tool and will not report power. I suppose you want to influence the power estimation carried out by Design Compiler by specifying the switching activity at the inputs. Please check the manual of design compiler on how you might be able to do this.
The report statements provided in the other answer have nothing to do with power estimation.
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