Dear Dilip Maske.

John Murphy is right. You should prepare some kind of rectifying electric junction on your semiconductor wafer (metal-semiconductor, conducting metal oxide-semiconductor, metal-insulator-semiconductor). You are interested in actual barrier capacitance of your structure, which depends on the properties of your semiconductor wafer. However, the measured capacitance will be different from the barrier capacitance because of the effect of series resistance and interface states. You can measure the capacitance of your structure at high frequency of the ac signal in order to eliminate the effect of interface states (in first approximation interface states can not follow the high frequency ac signal and thus do not contribute to the measured capacitance). But, in this case, you have to take into account the effect of series resistance and parasitic inductance of electric wires, which is proportional to the frequency of interface states. It is not so easy to correct your measured capacitance, because you need additional information.

I would recommend you to measure impedance spectroscopy of the rectifying structure based on your InSe wafer. You can find additional information about impedance spectroscopy from the following papers. I hope this information will help you.

Best regards.

I think you need to deposit a dielectric material on top of the semiconductor, and then some contact pads on top of that to form an MIS (metal-insulator-semiconductor) type capacitor. Typically this dielectric would be deposited by ALD, using a material such as hafnium oxide or aluminum oxide.

Dear Dilip Maske.

John Murphy is right. You should prepare some kind of rectifying electric junction on your semiconductor wafer (metal-semiconductor, conducting metal oxide-semiconductor, metal-insulator-semiconductor). You are interested in actual barrier capacitance of your structure, which depends on the properties of your semiconductor wafer. However, the measured capacitance will be different from the barrier capacitance because of the effect of series resistance and interface states. You can measure the capacitance of your structure at high frequency of the ac signal in order to eliminate the effect of interface states (in first approximation interface states can not follow the high frequency ac signal and thus do not contribute to the measured capacitance). But, in this case, you have to take into account the effect of series resistance and parasitic inductance of electric wires, which is proportional to the frequency of interface states. It is not so easy to correct your measured capacitance, because you need additional information.

I would recommend you to measure impedance spectroscopy of the rectifying structure based on your InSe wafer. You can find additional information about impedance spectroscopy from the following papers. I hope this information will help you.

Best regards.

Thank you V. Brus

Hello Dilip Maske,

You have mentioned that you have grown InSb wafer. Is it bulk inSb, or an epilayer on some other substrate like GaAs or InP? I believe that you like to do the C-V experiment to find out the doping density in your InSb.

In general, the easiest way to make the C-V measurement is to fabricate a metal-semiconductor Schottky barrier diode of known small area on the top of the semiconductor and a large area ohmic bottom contact. In this configuration it is possible to measure the ac depletion capacitance of the Schottky-barrier diode as a function of the applied reverse dc bias, which sets the depletion width in the semiconductor. In commercial C-meters a small-signal ac bias (typically 30-100 mV at 100 kHz or 1 MHz).

The problem for InSb is its very small bandgap and it is difficult to make a Schottky barrier diode at room temperatures. If you can give more details of the prolems you are facing, I may be able to suggest some solution.

You can take a silicon wafer sputter a metal and then deposit your InSb layer creating a MIS structure. C_V plot can give an important test on depletion region. It would be usefule make some C_V plot as a function of temperature to study the transport phenomena in your semiconductor.

Hi All,

I have a question about the MOS CV measurement of organic semiconductor, my structure is p++ Si / SiO2/ p typy organic semiconductor/ Ag, I use Aligent 4284A to do the capacitance-voltage scan, if I want to see accumulation of holes ( p type semiconductor) in negative DC bias, which electrode side should I connect to Lcur/Lpot? p++ Si side or Ag side? I just get confuse about how to connect Lcur/Lpot and Hcur/Lpot wires to the bottom and top electrodes, I got the CV result of device my structure as shown in the attached file, the curve is just what i expected, but i am not sure my connection is correct, can someone explain how to do the right connection in detail for me.Thanks in advance. 

Hi all

Positive probe of the lcr meter must be connected to the gate of the MOS 

Regards

I mean Ag side not the Si side

L means low or negative while h means high or positive . The h must be connected to the ag 

 Thanks for Abdulghefar Kamil Faiq. Actually I connect the Hcur/Hpot to Ag side, Lcur/Lpot to p++ Si side, and get the CV curve at high frequency (1 MHz) as shown above (green curve), however, I also measure CV curve at low frequency (100 Hz) using the same connection, the results at quite weird, at show below. at negative bias, accumulation region, it reaches the oxide areal capacitance (~11 nF/cm2) as expected, however, at positive bias, the capacitance reaches two times larger than the oxide areal capacitance, not oxide areal capacitance as expected in the case of MOS cap in low frequency, can someone explain this to me?

I think the larger capacitance must come from the capacitance in parallel with oxide capacitance, which should consider my device structure (also attached below, should consider the overlapping area of top layers), but why the larger capacitance didn't appear in the negative bias, this also a big question mark. any literature talking about this? I use SAM treated the SiO2 surface which can eliminate the trap state at the interface.  I am waiting for your help. Thank you.

Hi Abdulghefar Kamil Faiq,

I am still concerning about connection of CV test using 4284A, p++ Si is actually gate electrode in my OFET device, Ag is source (drain) electrode, so which side should I connect to Hcur/Hpot? I saw literature do the opposite connection in CV as we discussed previously(we think the Hcur/Hpot should connect to Ag side (source)), as seen in the attached image, it says Hcur/Hpot should connect to gate, which is p++ Si for my case. I would like to know your opinion. thank you.

 Hi Ke Pei

According to your diagram , it seems that the p++ is the gate of your system and must be connected to the H probe , but remember that your sample is just two terminal MOS and there is no need to call the gate terminal a source , you have just a gate and a bulk or substrae

Regards

Thanks Abdulghefar Kamil Faiq. the carriers are accumulated at SiO2/ seimiconductor interface, so the conductive part near the semiconductor can be treated as source or drain in two-terminal MIS structure