When you write a testbench, there are ways you can generate (random) test data or read test data from a file. Please go through the language reference manual. Best wishes.

Thank you so much for all your valuable advice. From my research and understanding, I created a Verilog A file that generates the different codes. Using those different codes, I am able to generate for 16 inputs by variations of codes.

I am planning to expand this model for my total 256*8 inputs.

Is there any trick/advice to deal with in Verilog A?

Thank you in advance.