I wish to study design of active inductor.How the transistors are to be sized to get the desired Quality factor and resonant frequency.Based on design equation for quality factor we can determine which transistor gm is the control parameter.But how to arrive at the requied gm value to do the design.I wish to know about the circuit design aspect whether we need to assume overdrive voltage for all transistors in circuit as starting point or gm/id design methodology is to be followed.
Dear Sir,
For an active inductor, you need 2 gyrators. So, basically, suppose you want an inductor between point A and B. You then need:
- 2 equal capacitors to ground, lets call their value C1 and C2, suppose they are between points C and D.
- You then need 2 OTA's, with transconductance gm1 and gm2.
(An OTA is a transconductance amplifier. Iout = gm * Vin).
- One ota input connected between A and B, output between C and D.
- One ota input connected between C and D, output between A and B.
- And there is your inductor between A and B. L = C/(gm1 * gm2)
(C is the capacitance between C and D. ie C1C2/(C1+C2))
- The Q factor is limited by the parasitics of the circuit. Please analyse yourself, and design the OTA and capacitors to meet your target requirements.
Henri.
Dear Lakshmi,
welcome,
You may need an other degree of freedom so that you can adjust Q , w0 and keep the power consumption as small as possible.
I would propose to to bias M1 with an additional current source from the the positive rail to the drain of the transistor. In this way you bias the two transistors independently and get more degree of freedom.
Best wishes
Dear Sir,
This circuit seems crude to me.
First, if it needs to resonate, you need to add capacitors on the gates of both transistors, as in this case LC = Cg1*Cg2/(gm1*gm2), which is more or less the intrinsic time constant of the MOS, and for sure way higher than the lower Ghz.
Second, your Q is limited by the resistors Rp and Rs. You need to reduce their value, and that seems not obvious. To increase Rs, you need to increase the length of the transistor. Rp seems fundamental tied to gm2, and that seems problematic.
Third, there are issues with noise behavior, power consumption and linearity.
Question: As you are operating in Ghz range, why dont you use passive inductor ?. They are available with Q of about 15 in these CMOS processes, and way better than (noise limited) active inductors.
Rp needs to be increased as it is shunting the inductor, while Rs needs to be made small as it is in series with the inductor for increasing the the quality factor.
As for the design to determine the the bias current and the dimensions of the transistor you have to relate them to the performance parameters, the resonance frequency and the quality factor and the power consumption to these independent parameters through the relation of the small signal parameters to the transistor w/l ratio and the DC drain bias current.
By formulating these equations you can solve them to get the unknowns.
This is one of the working appraoch.
Then after that you can trim these parameters by the CAD analysis tool.
Best wishes
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