Dear Sundaram,
welcome,
The logic design starts with describing the logic function with truth table or a Boolean expression.
fOR X-OR the Boolean expression can has the form
A x-or B com= AB + Acom B com complement=com,
So you have to build two CMOS invertes to complement A and B, the static CMOS inverter has the same circuit of the dynamic CMOS logic inverter. Even the bottom dynamic inverter consumes more transistors to prevent the evaluation during the precharge phase. Here we will use simle Dynamic CMOS gates which have one clocked precharge p-Mos transistor for a pull down block and we will nor use bottom transistor.
Accordingly We need two inverters for the A and B, then we need a logic block: AB + Acom B com which is A&B in parallel with Acom & B com.
Then we need to connect the output and or block to an a CMOS inverter.
Naturally there is another logic circuit satisfying the X-OR operation.
So, the number of the transistors= 6 for the inverters and 5 for the function logic gate. In case of static CMOS logic the number of the transistors= 6+ 8. So, the dynamic logic saves transistors.
Best wishes
Sundaram Muniasamy , Kindly see the attached picture. I guess it will enable you to design dynamic XOR gate
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