I suggest you to use MATLAB Simulink HDL Coder. Convert the file finally into VHDL/Verilog code which can be synthesisable in any FPGA (Spartan, Virtex etc.).
The following link will help you in basic HDL code generation process:
HDL code can be generated only if the blocks are supported by the HDL Coder. To find blocks and system objects supporting HDL code generation, please refer to the following page:
The advantage of porting your Matlab code into Simulink (and from there converting to VHDL) is that you can potentially simulate your VHDL code/blocks and test your system in Simulink, prior to porting to the FPGA. Limitation is that the number of blocks supported for HDL code generation is rather limited. For more complex functionalities you might need to build them up from more basic ones (that are supported).
I think better you write HDL instead of converting from MATLAB. Converting at RTL Level for any MATLAB code will not give correct functionality at hardware level.