For simplicity use oscilloscope or logic analyzer to know the frequency of a signal 

I have faced the same problem in my work.

Another method is by using ChipSope, which is a tool in Xilinx ISE software 

Hello all,

there is no "normal way" to access the clock frequency of the FPGA. Verilog (as well as VHDL) is independent of the clock - within the upper limit given by your logic delays. AND the system clock(s) is(are typically generated by means of PLL(s).

What you can do: measure the frequency of a known reference clock (e.g. the external clock) by means of a counter counting your system clock frequency. Thus you get the information about how many system clock cycles lie within 1 (or any other number of) reference clock cycle(s).

If you can afford an additional oscillator and/or require outstanding precision: create a rather slow reference clock (in the range of 1, 10, 100, 1000 ms) and apply the scheme described above. Here, counting for 1 reference clock cycle should be sufficient. Though it may create quite high counts - requiring adequate counter bit widths.

Dividing the FPGA system clock by a large value inorder to make the time peroid within the perception range of human vision, the clock time period can be measured manually. Once it is done, then by calculating using the offset by which the frequency is divided, one can get to know the exact clock frequency of the FPGA clock. Usually, clock frequencies of FPGAs are provided in their datasheets.

oscilloscope is the easiest one. It also help to proof your clocking in real time.

I agree with Mr. R.V.W Putra