Mainly, you need to define or determine exactly the dimensions of that inductor. then you need to define the substrate and metals properties. After, you can start drawing the inductor easily

Thanks Dr. Khalil, I defined the substrate, and draw the center tapped inductor and add the two port P1 and P2, but i do not know the CT connection is floating or grounded.

depending on your tap purpose, if you want it to be connected to ground, you can add a via to ground at the CT in the layout. However, you can still add a port then connect it to ground in the schematic. But if you want to connect the CT to some other components, then add a port there, then connect to the target in the schematic when doing EM co-simulation.

Thanks Dr. Huan Xu for your excellent answer

but i want to ask if the CT in the schematic connected to the drain of PMOS transistor, in the layout is it left floating. and if the CT in the schematic connected to the supply VDD, in the layout  is it connected o ground.

First, try to simulate your CT inductor alone (CT is floating). The next step, is to save its s parameters matrix. Now, you have a standard component of your center tapped inductor. You can generate it. Later, you can add it to any schematic circuit and simulate it gain to find if the performance is affected due to the insertion of your designed inductor. 

Thanks Dr. Khalil Yousef for your excellent answer.

if you dont add a backvia to ground at the CT in the layout, the CT in the layout remains floating even if it connected to vdd or gnd in the schematic.if you want to connect it to PMOS, add a port at the CT, then you can connect it to the pmos in the schematic later when you are doing cosimulation. refer to ADS help for more information on how to do em cosimulation

Thanks Dr. Huan Xu,

how i can make a via to ground, I designed the layout using 180 nm CMOS (TSMC), and the CT inductor is built in top layer, in other words where the gnd in which layer. is the gnd is M1 . if I connect Port the positive terminal is M6 but where the negative terminal (is it M1).

that depends on your substrate mapping, mostly, we treat MMIC substrate as microstrip or coplanar type, which needs a ground plane as a reference. In your case, you should decide your own ground plane, if your CMOS IC uses a whole layer(could be any metal layer, i.e. M1~M6) for ground or VCC, it could be treat as GND. But most importantly, choose the closest ground/vcc plane as your GND if you have more than one.