I am modelling an equaliser trained by linear RLS and LMS in a simple BPSK modulation system.
I found a problem that, the short length of equaliser, (e.g. equal to length of CIR), is not able to promise no error bit in noise-free environment. In contrast, the longer length of equaliser can reduce the propabability of error bit in the same environment.
However, the long equaliser has to cause complexity of circuit implementation.
In addition, the decision delay of equaliser also determines the performance of equaliser.
So, does anyone know that how to determine the length and decision delay of an equaliser?
Many thanks