Dear Purnendu,

Your question attracted me to see the data sheet of DSR4, i found that it is merely a switched capacitor sampler that can sample multiple channels with sampling speed from  700 MSPS to 5 GSPS . The samples are stored in a capacitor bank comprising 1024 cells  for each channel. These 1024 samples can be converted to digital signal by reading the samples and inputing them to an ADC chip with much lower speed than the sampling peed. 

The concept here is to acquire the signal and then analyse it in non real time.

Sampling must be made in real time but the analysis and display must not be in real time.

So you can use this chip to sample your signal at a speed greater than 2 x the maximum frequency of your signal of about 2Giga samples per second, and then read the stored samples in the chip imputing them  to a computer interfaced ADC chip with suitable conversion speed. Here according to data sheet, the peed is 33MHz.

FEATURES

Single 2.5 V power supply

Sampling speed 700 MSPS to 5 GSPS

8+1 channels with 1024 storage cells each

Cascading of channels or chips allows deeper

sampling depth

Differential inputs with 950 MHz bandwidth

Differential outputs for direct ADC

interfacing

Transparent mode for integrated triggering

Readout time: 30 ns * number of samples

Simultaneous reading and writing

Multiplexed or parallel analog outputs

Low power: 140 mW typical at 2 GSPS

(17.5 mW per channel)

Low integral nonlinearity:

0.5x10-3 at 1 V range

High SNR: 69 dB after offset correction

Low Noise: 0.35 mV after offset correction

I only reproduce the important specs in the data sheet of  DSR4:

The Domino Ring Sampler (DRS) is a switched capacitor

array (SCA) capable of sampling 9 differential input

channels at a sampling speed of 700 MSPS to 5 GSPS (6

GSPS for selected chips). The analog waveform is stored

in 1024 sampling cells per channel, and can be read out

after sampling via a shift register clocked at 33 MHz for

external digitization.

So, the chip is  merely an analog sample and hold circuit.

there are 1024 cells if writing speed is 5 GSPS but reading at 33 MSPS that means there is a dead time of 33 us - 204 ns ~32us after each cycle.

Dear Purnendu,

Yes,one samples 1024 samples in a time of Tsx 1024 and  convert them from analog to digital in Tcx 1024. Ts= i/5GHz and Tc= 1/ 33MHz. It turns out you can acquire only a portion of  the waveform  during the sampling time and overlook the rest of the waveform till the end of the conversion time. Then what do you deduced is okay.