After click Analyze Post-Place and Route static timing, the report summary says the following info:
Minimum period: 8.432ns{1} (Maximum frequency: 118.596MHz)
1、Now, my task is to better Maximum frequency, first I need to find the critical path, but I have the difficulty in identifying it in the timing report. Could anyone give me some guidance?
2、I have another question. What are the Timing Constraints in timing report for? Whether the critical path is related to the error constraint in the Timing Constraints?
The attached files give the detailed info about the timing report.
Thank you very much.
In addition, if I have found the critical path, how to improve the timing performance, namely improing Maximum Frequency?
In the design timing summary, the worst negative slack(WNS), which is highlighted click on it, after that it shows all the timing paths that are the intra-clock path and inter-clock path, it list paths based on timing requirement, the highest required is the critical path in the circuit.how to improve the timing performance based on the critical path.
Timing constraints are used to specify the timing characteristics of the design. Timing constraints may affect all internal timing interconnections, delays through logic and LUTs and between flip-flops or registers. Timing constraints can be either global or path-specific.
Take time to review the design timing analysis reports. Ensure that all paths are fully optimized. If paths are identified that are not meeting timing, make changes to adjust the way these paths are implemented.
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