You are talking about two separate problems here: Obtaining a WCET estimate and minimizing the WCET. For the former - WCET analysis - there are basically two approaches: static WCET analysis and measurement-based WCET analysis. Static WCET analysis is required if you want to have safe and tight bounds, and usually required in certifiable, safety-critical (hard) real-time systems. A model for the platform (processor, memory subsystem, ..) is necessary, so there is no general solution for arbitrary processors, as the others have mentioned. You can find an overview of the WCET problem in [1].

But as you are asking about a compiler, I assume you have a platform at hand for which you are building a compiler. Here you need tight integration of the compiler and a WCET analysis tool. Things are difficult because slight changes in the generated code may have a huge impact on the WCET (memory layout changes etc).

There were efforts in research to produce a compiler that reduces the WCET. One prominent example is WCC [2], but it is a closed-source compiler and AFAIK interfaces aiT at intermediate level.

In an effort to create a time-predictable platform within an EU FP7 project (http://www.t-crest.org), we used LLVM. Our processor was a dual-issue VLIW processor. The sources are on GitHub [3]. We interfaced aiT and also have a basic WCET analysis tool in the package.

Also Trimaran was used recently [4]. The researchers employed WCET-oriented hyperblock formation, and built their own IPET-based timing analyzer for a simple architecture model.

I hope this helps you to get started!

[1] The worst-case execution-time problem—overview of methods and survey of tools

http://dl.acm.org/citation.cfm?doid=1347375.1347389

[2] https://www.tuhh.de/es/esd/research/wcc.html

[3] https://github.com/t-crest

[4] A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation

http://dl.acm.org/citation.cfm?doid=2836331.2845083

https://github.com/t-crest

Article The worst-case execution-time problem - overview of methods ...

Article A Compile-Time Optimization Method for WCET Reduction in Rea...

I agree with Peter Breuer's very good points. If you want to get something, you will have to repeatedly measure to get a rough idea, because of all the wildly varying issues involved.

I guess it's not the compiler you are interested in here, but having the results for later comparison. If so, several processor architectures will give you an instruction to query for absolute time since the system is running. I used the example I am attaching (the link from Github) here for illustrating memory access overheads when reading data over a page long, for my Operating System classes; at the core of it all, you will find the following function:

unsigned long timestamp(){

     long tsc;

     asm volatile("rdtscp; "

         "shl $32, %%rdx; "

        "or %%rdx, %%rax"

        : "=a"(tsc)

        :

         : "%rcx", "%rdx"

    );

    return tsc;

}

That is, the rdtscp x86 assembler instruction will yield back a 64-bit number indicating how many clock cycles have happened since powerup.

Note that I am far from an assembly expert — I used as my sources for this information the other three links I'm presenting.

https://github.com/gwolf/sistop/blob/master/codigo/rendimiento_en_arreglo.c

https://ccsl.carleton.ca/~jamuir/rdtscpm1.pdf

http://www.strchr.com/performance_measurements_with_rdtsc

https://stackoverflow.com/questions/12631856/difference-between-rdtscp-rdtsc-memory-and-cpuid-rdtsc

You are talking about two separate problems here: Obtaining a WCET estimate and minimizing the WCET. For the former - WCET analysis - there are basically two approaches: static WCET analysis and measurement-based WCET analysis. Static WCET analysis is required if you want to have safe and tight bounds, and usually required in certifiable, safety-critical (hard) real-time systems. A model for the platform (processor, memory subsystem, ..) is necessary, so there is no general solution for arbitrary processors, as the others have mentioned. You can find an overview of the WCET problem in [1].

But as you are asking about a compiler, I assume you have a platform at hand for which you are building a compiler. Here you need tight integration of the compiler and a WCET analysis tool. Things are difficult because slight changes in the generated code may have a huge impact on the WCET (memory layout changes etc).

There were efforts in research to produce a compiler that reduces the WCET. One prominent example is WCC [2], but it is a closed-source compiler and AFAIK interfaces aiT at intermediate level.

In an effort to create a time-predictable platform within an EU FP7 project (http://www.t-crest.org), we used LLVM. Our processor was a dual-issue VLIW processor. The sources are on GitHub [3]. We interfaced aiT and also have a basic WCET analysis tool in the package.

Also Trimaran was used recently [4]. The researchers employed WCET-oriented hyperblock formation, and built their own IPET-based timing analyzer for a simple architecture model.

I hope this helps you to get started!

[1] The worst-case execution-time problem—overview of methods and survey of tools

http://dl.acm.org/citation.cfm?doid=1347375.1347389

[2] https://www.tuhh.de/es/esd/research/wcc.html

[3] https://github.com/t-crest

[4] A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation

http://dl.acm.org/citation.cfm?doid=2836331.2845083

https://github.com/t-crest

Article The worst-case execution-time problem - overview of methods ...

Article A Compile-Time Optimization Method for WCET Reduction in Rea...