The utility of memristances in SNN is that they can implement self-learning (as STDP) in a simple form without extra circuit area since the conductance between memristance nodes are plastic and dependent on the timing of the voltage through the memristor. If SNN is wanted to be implemented with CMOS technology only, then the inclusion of STDP would imply an extra circuitry if compared with mixed CMOS-memristance systems. Also, memristors are two-terminal devices that are occupying a lower area than conventional MOS transistors and the packaging is higher. The main drawback that I see to memristance devices is their low endurance. This is a technology that is not as mature as CMOS but I hope that in the near future the technology would be enhanced and higher endurance times could be reached.