Is there any way to implement the true random number generator in FPGA device either using HDL or as hardcore macros.
Note: LFSRs only generate the pseudo random numbers which is repetitive.
Google tells me:
https://people.csail.mit.edu/devadas/pubs/ches-fpga-random.pdf
Dear Sumathi,
I agree with Abdul, no deterministic machine as a FPGA or classic computer is able to generate a true random number generator using only an algorithm. Luckily, FPGAs can be used linked to an oscillator phase noise as an entropy source. Algorithms can be used to make pseudo-random number generators. There are many related papers about that, here you have some of the most relevant.
I hope they will be useful to you.
https://www.cosic.esat.kuleuven.be/publications/article-790.pdf
http://eprints.whiterose.ac.uk/103707/1/Camera_ready.pdf
Conference Paper Compact FPGA-based true and pseudo random number generators
Conference Paper An embedded true random number generator for FPGAs
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