Logic synthesizers generate logic level representations from RTL descriptions. The first step towards this is derive the Boolean expressions for the internal and output nodes. I need to generate a file containing all these Boolean equations. Are there any tools that generate such file. Of course this can be done manually, but this is tedious and error prone especially for large RTL codes.
Thank you for your prompt answer
RTL viewer gives the boolean expression for each cell, one by one. I need the full set of boolean equations for all cells of the design in on integrated file (edif file say). I need this file to port the design to PLD device. Assembling this integrated file by hand would be tedious.
Thanks Dr. Dreher
Yes. You are right. There is a tool from Atmel (Atmel prochip) that does this"compilation". But, unfortunately it does not support my target PLD !. My question is exactly about a tool chain that can compile from .vhd (or .v) to .pld. Alternatively, from .vhd (or .v) to .edif
Thanks Dr. Murthy
Yes the required boolean expressions are certainly generated (embedded) in the all logic synthesis tools (Quartus II, ISE, DC, ...etc.). But, as far as I managed to get from these tools, the full set of these boolean expressions is not outputted in a handy way. extraction is tedious I mentioned earlier.
I do not like the tone of some of the comments so far passed. I am not also going to indulge in facebook-like dialogues.
Research gate should remain a forum for dignified discussions with mutual respect. And, remember, your answers are not that vital anyway.
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