hope all of you are doing well, unfortunately there is no reliable document for calculating the DAC switching energy. Based on the different equations I reach to different results. I am totally confused...
Unfortunately it does not help. I am totally confused for calculating the dynamic energy consumption of switching from one logic state to the next logic state.
The dynamic energy consumption is exactly the above: charging/discharging the parasitic capacitances. For CMOS implementations, your equations will hold a frequency component plus a VCC2 component. While the static energy consumption should be negligible. (OK - in the latest technologies the static consumption is rising again due to higher leakage currents while the dynamic consumption goes down with lower suply voltages and lower parasitic capacitances.)
The energy consumption in the DAC is proportion to the voltage change on the two different stage. Unfortunately the provided information you mentioned are so overall and superficial about the CMOS technologies. I need more specific answer.