I create patterns (several micrometers) on hBN flakes on a Si/SiO2 substrate using EBL (100kV). I find cracking / extra lines emerging from my pattern after development. I guess it is due to substrate charging issue, so I have tried ZEP and conducting polymer. However, the problem cannot be completely resolved. Now I am wondering it is due to substrate charging. Could it arise from bias induced stress on PMMA/ZEP and lead to cracks during development.
Dear Ting Fung,
Typically, using Si substrate and the acceleration voltage of 100kV should not give rise to significant charging, given that your exposed sample or wafer has good electrical contact with the stage.
Thanks, Philip. We have resolved the problem. We modify our pattern design and make all sharp corner rounded. With rounded corners, I don't see additional lines anymore.
One more alternative for development. See the following paper. https://nano.yale.edu/sites/default/files/files/pmma_develop_ipa_water.pdf
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