If you use the answers from external resources like ResearchGate in your project thesis please also remember to set a reference to it. Otherwise I will reject your work.

Regards Erik Markert, Project advisor

JTAG is a protocol to do among other things boundary scan. Its also used for other things, like eg processor debug interface, debug interface for analog circuit.

VHDL together with Verilog are hardware description languages. (Modelsim can do VHDL, and also Verilog. VHDL is mainly used in Europe, Verilog elsewhere, mainly in the United States. There are some differences between the languages, which I will not discuss here.) VHDL is strongly types (like pascal in software), verilog not (like C). Overall, verilog is the dominant language. In Verilog, you can use gated clocks, if you do in VHDL, you create a mess. For that reason, I prefer verilog.

To describe the JTAG interface in VHDL (or Verilog - not much difference), you need to have an idea what hardware you want to design. The process is you read the JTAG spec, make up what your circuit  should do to meet this spec, and then describe this in VHDL or Verilog.  (its like making software.) After making your description, you debug it using Modelsim. Modelsim is a simulator, which means you describe in Modelsim (also in Vhdl or Verilog or C) what signals you want to apply to your circuit, then run Modelsim, and it will show you what the circuit does when you apply these stimuli.

It is tool for debug online when you have coded a VHDL in the circuit description

Check out these two links - you can quickly learn a lot from them:

http://www.gojtag.com/package

http://www.fpga4fun.com/JTAG.html