Hello;
At this moment, I can wrote some basic code in verilog , and I want now to know what is the difference between wire and reg to understand them , I read that wire is like real wire not stored data, but I can store data in wire (assign a = 1'b1) so could you please tell me how can i visually know how to understand that and put this idea in code?
thank you
Hi,
From my understanding, it is a very important difference for basic port connection rules as well (see attached), from the hierarchical design perspective in VHDL.
"Registers represent data storage elements. Registers retain value until another value is placed onto them. Do not confuse the term registers in Verilog with hardware registers built from edge-triggered flipflops in real circuits. In Verilog, the term register merely means a variable that can hold a value. Unlike a net, a register does not need a driver. Verilog registers do not need a clock as hardware registers do. Values of registers can be changed anytime in a simulation by assigning a new value to the register."
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted.
end
"A net represent connections between hardware elements. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to."
"Nets are declared primarily with the keyword wire. Nets are one-bit values by default unless they are declared explicitly as vectors. The terms wire and net are often used interchangeably. The default value of a net is z (except the trireg net, which defaults to x). Nets get the output value of their drivers. If a net has no driver, it gets the value z."
wire a; // Declare net a for the above circuit
wire b,c; // Declare two wires b,c for the above circuit
wire d = 1'b0; // Net d is fixed to logic value 0 at declaration.
For example, I take the Figure 4.2 for the citation below. For port definitions (according to connect.jpg) it should go like:
// Declarations of wire, reg, and other variables
wire q, qbar;
reg set, reset;
I hope this could be helpful. This book made a great reference for me as well.
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition
By Samir Palnitkar
what is the difference between
reset = 1'b1;// from reg
and
wire d = 1'b0; // from wire
both can have value , so how can reg retain data but wire cant?
Well,
According to the data type nature, which is Verilog's syntax in essence. Registers can retain data until it is changed by a specific procedure while nets are driven at all times (the wire construct is based on gates, if no drivers are set, the default value is z), that is the very language definition.
There is also a nice tutorial on this:
https://blogs.mentor.com/verificationhorizons/blog/2013/05/03/wire-vs-reg
I hope this info is useful
reg is synthesized as a register (flip flop)
in your example: reset = 1'b1;
reset register stores the value "1"
wire is synthesized as wire
in your example: wire d = 1'b0;
"0" will be the seed value of where you connect the cable (d) (and this can be lost at any time)
hey before knowing more about reg & wire, please know about blocking and non-blocking assignments and its importances. If you understand them, then you will answer your own question, "what is the difference between reg and wire?"
I thought that reg and wire the first stage to understand verilog and the second is blocking and nonblocking !!
could you ( Madhu Babu) please tell me more about them
Miguel Duarte-Villaseñor: how can wire loose its value?in real hardware or in coding. this is that i cant understand
Hey hayder Al-Amily,
Bottom line: wire and blocking assignments are linked together, where reg and non-blocking assignments are linked to get a good design in hardware circuitry.
eg:
reset = 1'b1;// from reg
and
wire d = 1'b0; // from wire
In this eg. there is no difference you use blocking assignments for both reg and wire. both doesn't store value for future use but this value can be used instantly.
Reg can store value as flipflop or just pass the value, it depends on the situation and the way you are assessing in your code.
Wire can pass value but can't store value.
So, reg can be used as wire, but wire can never be used as reg.
Synthesiser decides whether "reg" should be stored for future or just pass the value. it purely depends on the way you are assessing values either with blocking or non-blocking assignments.
pls refer any basic verilog book to get a good idea on these concepts.
wire is a physical wire when your verilog code is synthesized.
reg is a memory element (flip-flop or latch)
but for practical purpose, a verilog signal/identifier needs to be declared as "reg" when it is used on the left hand side (LHS) of the equatiion inside a behavioral verilog statement i.e. used in "initial" or "always" statement. "wire" on the other hand is used in an "assign" statement.
example
reg a;
initial a = 0;
reg b;
always @(posedge clk) b
REG IS NOT A FLIP FLOP.
reg is a verilog data type that can be synthesized into either sequential or combinational logic depending on how you code it. This is verilog 101. It appears from the posts above that very few people actually know verilog.
Example of a reg that will be synthesized as combinational logic:
reg myreg;
always @ (*) begin
myreg = 1'b0;
end
Example of a reg that will be synthesized as sequential logic (flip flop):
reg myreg;
always @ (posedge clk) begin
myreg
Actually, reg and wire is pretty similar. It depends on how you use it.
Wire is used as combinational logic. You can assign it, e.g. assign a = 1'b1. In this case, the one which holds the value is 1'b1.
Reg can be used as either combinational or sequential logic. In always@ block, you have to use reg to assign for a value, e.g. '=' or '
"net" represent connections between hardware elements (default value is Z, i.e. high impedance ).
"reg" represent data storage element. It retains value until another value is placed onto them ( default value is X, i.e. don't care).
Almost all answers are wrong. Check the correct answer of Samuel Pagliarini on May 16, 2016.
The wire is used for a continuous assignment whereas reg is used in a procedural assignment.
You use wire when the output of a logic element is connected to an input of another logic element while reg is a variable in verilog which is used in a procedural assignment statement such as sensitivity list within an always block,it denotes register
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